S25FL128SDSNFVC10 查看數據表（PDF） - Cypress Semiconductor
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S25FL128SDSNFVC10
Cypress Semiconductor
S25FL128SDSNFVC10 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
7.5.7
Password Register (PASS)
Related Commands: Password Read (PASSRD E7h) and Password Program (PASSP E8h).
Table 7.18 Password Register (PASS)
Bits
Field Name
Function
63 to 0
PWD
Hidden Password
Type
OTP
Default State
FFFFFFFF-FFFFFFFFh
Description
Non-volatile OTP storage of 64 bit password. The password is no longer
readable after the password protection mode is selected by programming
ASP register bit 2 to zero.
7.5.8
PPB Lock Register (PPBL)
Related Commands: PPB Lock Read (PLBRD A7h, PLBWR A6h)
Table 7.19 PPB Lock Register (PPBL)
Bits
7 to 1
Field Name
RFU
Function
Reserved
Type
Volatile
Default State
00h
0
PPBLOCK
Protect PPB Array
Volatile
Persistent Protection Mode = 1
Password Protection Mode = 0
Description
Reserved for Future Use
0 = PPB array protected until next power cycle or
hardware reset
1 = PPB array may be programmed or erased.
7.5.9
PPB Access Register (PPBAR)
Related Commands: PPB Read (PPBRD E2h)
Table 7.20 PPB Access Register (PPBAR)
Bits
Field Name
Function
Type
7 to 0
PPB
Read or Program per
sector PPB
Non-volatile
Default
State
FFh
Description
00h = PPB for the sector addressed by the PPBRD or PPBP
command is programmed to 0, protecting that sector from program
or erase operations.
FFh = PPB for the sector addressed by the PPBRD or PPBP
command is erased to 1, not protecting that sector from program or
erase operations.
7.5.10
DYB Access Register (DYBAR)
Related Commands: DYB Read (DYBRD E0h) and DYB Program (DYBP E1h).
Table 7.21 DYB Access Register (DYBAR)
Bits
7 to 0
Field Name
Function
Type
DYB
Read or Write per
sector DYB
Volatile
Default State
FFh
Description
00h = DYB for the sector addressed by the DYBRD or DYBP command is cleared
to 0, protecting that sector from program or erase operations.
FFh = DYB for the sector addressed by the DYBRD or DYBP command is set to 1,
not protecting that sector from program or erase operations.
7.5.11
SPI DDR Data Learning Registers
Related Commands: Program NVDLR (PNVDLR 43h), Write VDLR (WVDLR 4Ah), Data Learning Pattern Read (DLPRD 41h).
The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as an 8-bit Volatile Data
Learning Register (VDLR). When shipped from Cypress, the NVDLR value is 00h. Once programmed, the NVDLR cannot be
reprogrammed or erased; a copy of the data pattern in the NVDLR will also be written to the VDLR. The VDLR can be written to at
any time, but on reset or power cycles the data pattern will revert back to what is in the NVDLR. During the learning phase described
in the SPI DDR modes, the DLP will come from the VDLR. Each IO will output the same DLP value for every clock edge. For
example, if the DLP is 34h (or binary 00110100) then during the first clock edge all IO’s will output 0; subsequently, the 2nd clock
edge all I/O’s will output 0, the 3rd will output 1, etc.
When the VDLR value is 00h, no preamble data pattern is presented during the dummy phase in the DDR commands.
Document Number: 001-98283 Rev. *I
Page 55 of 144
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