S25FL128SAGMHVB01 查看數據表（PDF） - Cypress Semiconductor

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S25FL128SAGMHVB01

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

9. Commands

All communication between the host system and S25FL128S and S25FL256S memory devices is in the form of units called

commands.

All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands

may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All

instruction, address, and data information is transferred serially between the host system and memory device.

All instructions are transferred from host to memory as a single bit serial sequence on the SI signal.

Single bit wide commands may provide an address or data sent only on the SI signal. Data may be sent back to the host serially on

SO signal.

Dual or Quad Output commands provide an address sent to the memory only on the SI signal. Data will be returned to the host as a

sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3.

Dual or Quad Input/Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four bit (nibble)

groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0,

IO1, IO2, and IO3.

Commands are structured as follows:

Each command begins with an eight bit (byte) instruction.

The instruction may be stand alone or may be followed by address bits to select a location within one of several address

spaces in the device. The address may be either a 24-bit or 32-bit byte boundary address.

The Serial Peripheral Interface with Multiple IO provides the option for each transfer of address and data information to be

done one, two, or four bits in parallel. This enables a trade off between the number of signal connections (IO bus width) and

the speed of information transfer. If the host system can support a two or four bit wide IO bus the memory performance can be

increased by using the instructions that provide parallel two bit (dual) or parallel four bit (quad) transfers.

The width of all transfers following the instruction are determined by the instruction sent.

All sIngle bits or parallel bit groups are transferred in most to least significant bit order.

Some instructions send instruction modifier (mode) bits following the address to indicate that the next command will be of the

same type with an implied, rather than an explicit, instruction. The next command thus does not provide an instruction byte,

only a new address and mode bits. This reduces the time needed to send each command when the same command type is

repeated in a sequence of commands.

The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before

read data is returned to the host.

Read latency may be zero to several SCK cycles (also referred to as dummy cycles).

All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted into the device

with the most significant byte first. All data is transferred with the lowest address byte sent first. Following bytes of data are

sent in lowest to highest byte address order i.e. the byte address increments.

All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. The

embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an

embedded operation. These are discussed in the individual command descriptions. While a program, erase, or write operation

is in progress, it is recommended to check that the Write-In Progress (WIP) bit is 0 before issuing most commands to the

device, to ensure the new command can be accepted.

Depending on the command, the time for execution varies. A command to read status information from an executing

command is available to determine when the command completes execution and whether the command was successful.

Document Number: 001-98283 Rev. *I

Page 63 of 144

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