S25FL128SAGMFN200 查看數據表（PDF） - Cypress Semiconductor
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S25FL128SAGMFN200
Cypress Semiconductor
S25FL128SAGMFN200 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Figure 9.35 Dual I/O Read Command Sequence (4-byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b)
CS#
SCK
IO0
IO1
01
76
2345
8 cycles
Instruction
5432
678
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
16 cycles
32 Bit Address
4 cycles
Mode
2 cycles
Dummy
4 cycles
Data 1
Data 2
1 0 30
20
2064
6 420642
31
31
3175
7 531753
Figure 9.36 Continuous Dual I/O Read Command Sequence (4-byte Address, BCh or BBh [ExtAdd=1], EHPLC=10b)
CS#
0
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SCK
4 cycles
Data N
IO0 6 4 2 0
IO1 7 5 3 1
16 cycles
32 Bit Address
30
20
31
31
4 cycles
Mode
2 cycles
Dummy
4 cycles
Data 1
6 420
6 420
7 531
7 531
4 cycles
Data 2
6420
7531
9.4.6
Quad I/O Read (QIOR EBh or 4QIOR ECh)
The instruction
EBh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
EBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
ECh is followed by a 4-byte address (A31-A0)
The Quad I/O Read command improves throughput with four I/O signals — IO0-IO3. It is similar to the Quad Output Read command
but allows input of the address bits four bits per serial SCK clock. In some applications, the reduced instruction overhead might allow
for code execution (XIP) directly from S25FL128S and S25FL256S devices. The QUAD bit of the Configuration Register must be set
(CR Bit1=1) to enable the Quad capability of S25FL128S and S25FL256S devices.
The maximum operating clock frequency for Quad I/O Read is 104 MHz.
For the Quad I/O Read command, there is a latency required after the mode bits (described below) before data begins shifting out of
IO0-IO3. This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to access data at the initial
address. During latency cycles, the data value on IO0-IO3 are “don’t care” and may be high impedance. The number of dummy
cycles is determined by the frequency of SCK and the latency code table (refer to Table 7.12, Latency Codes for SDR Enhanced
High Performance on page 51). There are different ordering part numbers that select the latency code table used for this command,
either the High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC) table. The number of dummy cycles
is set by the LC bits in the Configuration Register (CR1). However, both latency code tables use the same latency values for the
Quad I/O Read command.
Following the latency period, the memory contents at the address given, is shifted out four bits at a time through IO0-IO3. Each
nibble (4 bits) is shifted out at the SCK frequency by the falling edge of the SCK signal.
The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address
in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read
instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back
to 000000h, allowing the read sequence to be continued indefinitely.
Document Number: 001-98283 Rev. *I
Page 89 of 144
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