S25FL128SDPMHVB11 查看數據表（PDF） - Cypress Semiconductor
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S25FL128SDPMHVB11
Cypress Semiconductor
S25FL128SDPMHVB11 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
If less than a page of data is sent to the device, these data bytes will be programmed in sequence, starting at the provided address
within the page, without having any affect on the other bytes of the same page.
For optimized timings, using the Page Program (PP) command to load the entire page size program buffer within the page boundary
will save overall programming time versus loading less than a page size into the program buffer.
The programming process is managed by the flash memory device internal control logic. After a programming command is issued,
the programming operation status can be checked using the Read Status Register-1 command. The WIP bit (SR1[0]) will indicate
when the programming operation is completed. The P_ERR bit (SR1[6]) will indicate if an error occurs in the programming operation
that prevents successful completion of programming.
Figure 9.53 Page Program (PP) Command Sequence (3-byte Address, 02h)
CS#
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction
24-Bit
Address
Data Byte 1
23 22 21
MSB
321076543210
MSB
CS#
SCK
SI
CS#
40 41 42 43 44 45 46 47 48 49 59 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 512
7654321076543210
MSB
MSB
76543210
MSB
Figure 9.54 Page Program (4PP) Command Sequence (4-byte Address, 12h)
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47
Instruction
32-Bit
Address
Data Byte 1
31 30 29
MSB
321076543210
MSB
CS#
SCK
SI
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Data Byte 2
Data Byte 3
Data Byte 512
7654321076543210
MSB
MSB
76543210
MSB
Document Number: 001-98283 Rev. *I
Page 99 of 144
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