SST39VF1602C-70-4C-MAKE(2010) 查看數據表（PDF） - Silicon Storage Technology
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SST39VF1602C-70-4C-MAKE Datasheet PDF : 33 Pages
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Data Sheet
ADDRESS AMS-0
CE#
OE#
WE#
DQ6 and DQ2
TCE
TOEH
TOE
Note:
AMS = Most significant address
AMS = A19
FIGURE 10: Toggle Bits Timing Diagram
16 Mbit Multi-Purpose Flash Plus
SST39VF1601C / SST39VF1602C
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
1380 F07.0
ADDRESSES
SIX-BYTE CODE FOR CHIP-ERASE
555
2AA
555
555
2AA
555
TSCE
CE#
OE#
WE#
RY/BY#
TOEH
TBY
TBR
DQ15-0
XXAA XX55
XX80 XXAA XX55
XX10
VALID
1380 F31.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchange-
able as long as minimum timings are met. (See Table 16).
WP# must be held in proper logic state (VIH) 1µs prior to and 1µs after the command sequence.
X can be VIL or VIH, but no other value.
FIGURE 11: WE# Controlled Chip-Erase Timing Diagram
©2010 Silicon Storage Technology, Inc.
18
S71380-04-000
05/10
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