ST72F63BE4M1 查看數據表（PDF） - STMicroelectronics

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ST72F63BE4M1

Low speed USB 8-bit MCU family with up to 32 KB Flash/ROM, DFU capability, 8-bit ADC, WDG, timer, SCI and I²C

STMicroelectronics 

On-chip peripherals

ST7263Bxx

11.5.5

Low power modes

Table 41. Low power modes

Mode

Description

No effect on I²C interface.

WAIT

I²C interrupts cause the device to exit from Wait mode.

HALT

I²C registers are frozen.

In Halt mode, the I²C interface is inactive and does not acknowledge data on the bus. The

I²C interface resumes operation when the MCU is woken up by an interrupt with “exit from

Halt mode” capability.

11.5.6

Interrupts

Figure 49. Event flags and interrupt generation

BTF

ITE

ADSL

SB

AF

STOPF

ARLO

BERR

(1)

INTERRUPT

EVF

1. EVF can also be set by EV6 or an error from the SR2 register.

Table 42. Interrupts

Interrupt event

Event

flag

Enable

control

bit

End of Byte Transfer Event

Address Matched Event (Slave mode)

Start Bit Generation Event (Master mode)

Acknowledge Failure Event

Stop Detection Event (Slave mode)

Arbitration Lost Event (Multimaster configuration)

Bus Error Event

BTF

ADSL

SB

AF

ITE

STOPF

ARLO

BERR

Exit

from

Wait

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Exit

from

Halt

No

No

No

No

No

No

No

The I²C interrupt events are connected to the same interrupt vector (see Interrupts chapter).

They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the

CC register is reset (RIM instruction).

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Doc ID 7516 Rev 8

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