ST7FDALI 查看數據表（PDF） - STMicroelectronics

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ST7FDALI

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI

STMicroelectronics 

ST7DALI

Date Revision

Description of Changes

19-Nov-2004

Revision number incremented from 1.3 to 2.0 due to Internal Document Management System

change

Added FASTROM devices

Modified Caution to pin n°12 (SO20) or pin n°7 (DIP20) and added caution to PB0 and PB1 in

Table 1 on page 7

Changed Caution in section 4.4 on page 13

Changed 1st sentence in section 4.5.1 on page 14

Replaced CRSR register by SICSR register in section 7.6.3 on page 32

Added note in section 7.6.1 on page 29

Changed “Output Compare Mode” on page 57 and note 1 in section 11.2.6 on page 60

Replaced FFh by FFFh in the description of OVF bit in section 11.2.6 on page 60

Replaced ICAP1 pin by LTIC Pin in section 11.3.3.3 on page 66

Changed “An interrupt is generated if SPIE = 1 in the SPICSR register” to “An interrupt is gen-

erated if SPIE = 1 in the SPICR register” in description of OVR and MODF bits in section 11.5.8

on page 87

Removed references to “-40°C to +125°C” temperature range in section 13 on page 100

Changed section 13.3 on page 102

Changed note 2 in section 13.2.1 on page 101

Added one row in section 13.2.2 on page 101 (PB0 and PB1)

Added note 5 in section 13.4.1 on page 108

Added VDD row in section 13.6.3 on page 111

Changed section 13.7 on page 112

Added caution to Figure 69 on page 114

Added VIL min value and VIH max value in section 13.8.1 on page 114 and in section 13.9.1

on page 119

Modified “Asynchronous RESET Pin” on page 119 (Figure 86 and Figure 87)

Updated ADC accuracy table values on page 124

Changed values in ADC Characteristics table on page 126

2.0

Added “NEGATIVE INJECTION IMPACT ON ADC ACCURACY” on page 138

Changed Table 24, “List of valid option combinations,” on page 131: PLLx4x8 selection when

PLL offAdded “ST7DALI FASTROM MICROCONTROLLER OPTION LIST (Last update: No-

vember 2004)” on page 133

Updated Figure 65. Typical IDD in WAIT vs. fCPU with correct data

Added data for Fcpu @ 1MHz into Section 13.4.1 Supply Current table.

Reset delay in section 11.1.3 on page 51 changed to 30µs

Altered note 1 for section 13.2.3 on page 101 removing references to RESET

Removed sentence relating to an effective change only after overflow for CK[1:0], page 60

MOD00 replaced by 0Ex in Figure 36 on page 57

Added Note 2 related to Exit from Active Halt, section 11.2.5 on page 59

Added illegal opcode detection to page 1, section 7.6 on page 29, section 12 on page 94

Clarification of Flash read-out protection, section 4.5.1 on page 14

Added note 4 and description relating to Total Percentage in Error and Amplifier Output Offset

Variation to the ADC Characteristics subsection and table, page 126

Added note 5 and description relating to Offset Variation in Temperature to ADC Characteris-

tics subsection and table, page 126

FPLL value of 1MHz quoted as Typical instead of a Minimum in section 13.3.4.1 on page 104

Updated FSCK in section 13.10.1 on page 121 to FCPU/4 and FCPU/2

Corrected FCPU in SLOW and SLOW WAIT modes in section 13.4.1 on page 108

Max values updated for ADC Accuracy, page 124

Notes indicating that PB4 cannot be used as an external interrupt in HALT mode, section 16.6

on page 138 and Section 8.3 PERIPHERAL INTERRUPTS

Changed section 11.5.2 on page 79

Changed section 11.5.3.3 on page 82

Removed “optional” referring to VDD in Figure 4 on page 13

Changed FMP_R option bit description in section 15.1 on page 130

Added “CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE” on page 138

Changed “DEVELOPMENT TOOLS” on page 134

Changed Figure 41 on page 70: fCPU instead of 8MHz fCPU

140/141

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