PSD834F2VA-15MIT 查看數據表（PDF） - STMicroelectronics
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PSD834F2VA-15MIT Datasheet PDF : 128 Pages
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AC/DC parameters
PSD8XXFX
Table 50.
Symbol
CPLD macrocell Synchronous clock mode timing (5 V devices) (continued)
Parameter
Conditions
-70
-90
Min Max Min Max
-15
Min Max
Fast
PT
Turbo Slew
rate
Unit
Aloc off
(1)
tARD
CPLD array
delay
Any macrocell
11
16
22 + 2
ns
tMIN
Minimum clock
period(2)
tCH+tCL
12
20
30
ns
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.
) Table 51.
uct(s Symbol
CPLD macrocell synchronous clock mode timing (3 V devices)
Parameter
Conditions
-12
-15
-20
Min Max Min Max Min Max
PT
Aloc
Turbo Slew
rate
off (1)
Unit
olete Prod fMAX
ct(s) - Obs tS
u tH
rod tCH
P tCL
lete tCO
so tARD
ObtMIN
Maximum
frequency
External feedback
1/(tS+tCO)
22.2
18.8
15.8
Maximum
frequency
Internal feedback 1/(tS+tCO–10)
28.5
23.2
18.8
(fCNT)
Maximum
frequency
Pipelined data
1/(tCH+tCL)
40.0
33.3
31.2
Input setup time
20
25
30
+4
Input hold time
0
0
0
Clock high time
Clock input 15
15
16
Clock low time
Clock input 10
15
16
Clock to output
delay
Clock input
25
28
33
CPLD array delay Any macrocell
25
29
33 + 4
Minimum clock
period(2)
tCH+tCL
25
29
32
+ 20
MHz
MHz
MHz
ns
ns
ns
ns
– 6 ns
ns
ns
1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.
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Doc ID 7833 Rev 7
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