PSD833F4A-90UIT 查看數據表（PDF） - STMicroelectronics
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PSD833F4A-90UIT Datasheet PDF : 128 Pages
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AC/DC parameters
PSD8XXFX
Table 52. CPLD macrocell asynchronous clock mode timing (5 V devices) (continued)
Symbol Parameter
Conditions
-70
-90
Min Max Min Max
-15
Min Max
PT Turbo Slew
Aloc off rate
Unit
tCOA
Clock to
output delay
21
30
tARDA
CPLD array
delay
Any macrocell
11
16
37
+ 10 – 2 ns
22 + 2
ns
tMINA
Minimum
clock period
1/fCNTA
16
28
39
ns
) Table 53. CPLD macrocell Asynchronous clock mode timing (3 V devices)
uct(s Symbol Parameter
Conditions
-12
Min Max
-15
Min Max
-20
Min Max
PT Turbo Slew
Aloc off rate
Unit
solete Prod fMAXA
uct(s) - Ob tSA
rod tHA
P tCHA
te tCLA
ole tCOA
ObstARD
Maximum
frequency
External
feedback
1/(tSA+tCOA)
21.7
19.2
16.9
MHz
Maximum
frequency
Internal
feedback
(fCNTA)
1/(tSA+tCOA–10)
27.8
23.8
20.4
Maximum
frequency
1/(tCHA+tCLA)
33.3
27
24.4
Pipelined data
MHz
MHz
Input setup time
10
12
13
+ 4 + 20
ns
Input hold time
12
15
17
ns
Clock high time
17
22
25
+ 20
ns
Clock low time
13
15
16
+ 20
ns
Clock to output
delay
36
40
46
+ 20 – 6 ns
CPLD array
delay
Any macrocell
25
29
33 + 4
ns
tMINA
Minimum clock
period
1/fCNTA
36
42
49
ns
104/128
Doc ID 7833 Rev 7
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