PSD814F4A-70UT 查看數據表（PDF） - STMicroelectronics
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PSD814F4A-70UT Datasheet PDF : 128 Pages
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PSD8XXFX
AC/DC parameters
1. The whole memory is programmed to 00h before erase.
2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
Figure 46. Peripheral I/O READ timing
ALE /AS
A /D BUS
ADDRESS
DATA VALID
tAVQV (PA)
tSLQV (PA)
t(s) CSI
uc tRLQV (PA)
tQXRH (PA)
tRHQZ (PA)
d RD
tRLRH (PA)
te Pro tDVQV (PA)
sole DATA ON PORT A
AI02897
Ob Table 62. Port A Peripheral Data mode READ timing (5 V devices)
t(s) - Symbol
Parameter
Conditions
-70
-90
-15
Turbo
Unit
Min Max Min Max Min Max off
duc tAVQV–PA
ro tSLQV–PA
te P tRLQV–PA
Address valid to data valid
CSI valid to data valid
RD to data valid
RD to data valid 8031 mode
(1)
(2)(3)
37
39
45 + 10 ns
27
35
45 + 10 ns
21
32
40
ns
32
38
45
ns
ole tDVQV–PA
stQXRH–PA
ObtRLRH–PA
Data In to data out valid
RD data hold time
RD pulse width
22
30
38
ns
0
0
0
ns
(2)
27
32
38
ns
tRHQZ–PA
RD to data high-Z
(2)
23
25
30
ns
1. Any input used to select port A Data Peripheral mode.
2. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
3. Data is already stable on port A.
Doc ID 7833 Rev 7
111/128
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