PSD833F5A-90JIT 查看數據表（PDF） - STMicroelectronics

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PSD833F5A-90JIT

Flash in-system programmable (ISP) ipherals for 8-bit MCUs, 5 V

STMicroelectronics 

PSD architectural overview

PSD8XXFX

The PSD also has some bits that are configured at run-time by the MCU to reduce power

consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches

its outputs and goes to sleep until the next transition on its inputs.

Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD

to reduce power consumption. Please see Section 17: Power management for more details.

Table 5. JTAG SIgnals on port C

Port C pins

JTAG signal

PC0

TMS

PC1

TCK

PC3

TSTAT

) PC4

TERR

t(s PC5

TDI

uc PC6

TDO

rod Table 6. Methods for programming different functional blocks of the PSD

te P Functional block

JTAG

programming

Device

programmer

IAP

ole Primary Flash memory

Yes

Yes

Yes

bs Secondary Flash memory

Yes

Yes

Yes

O PLD array (DPLD and CPLD)

Yes

Yes

No

Obsolete Product(s) - PSD configuration

Yes

Yes

No

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Doc ID 7833 Rev 7

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