PSD833F3A-20UI 查看數據表（PDF） - STMicroelectronics
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PSD833F3A-20UI Datasheet PDF : 128 Pages
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Initial delivery state
20 Initial delivery state
PSD8XXFX
When delivered from ST, the PSD device has all bits in the memory and PLDs set to ’1.’ The
PSD Configuration register bits are set to ’0.’ The code, configuration, and PLD logic are
loaded using the programming procedure. Information for programming the device is
available directly from ST. Please contact your local sales representative.
Table 36. JTAG Enable register(1)
Bit
Name
Description
t(s) Bit 0
JTAG_Enable
0=
off
JTAG port is disabled.
1=
on
JTAG port is enabled.
c Bit 1
X
0 Not used, and should be set to zero.
du Bit 2
X
0 Not used, and should be set to zero.
ro Bit 3
X
0 Not used, and should be set to zero.
P Bit 4
X
0 Not used, and should be set to zero.
te Bit 5
X
0 Not used, and should be set to zero.
ole Bit 6
X
0 Not used, and should be set to zero.
bs Bit 7
X
0 Not used, and should be set to zero.
O 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are
- dedicated by an NVM Configuration bit (via PSDsoft Express). However, Reset (RESET) prevents or
Obsolete Product(s) interrupts JTAG operations if the JTAG enable register is used to enable the JTAG signals.
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Doc ID 7833 Rev 7
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