STM32F303RCT7 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

STM32F303RCT7

ARM Cortex-M4F 32b MCU+FPU, up to 256KB Flash+48KB SRAM 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V operation

STMicroelectronics 

STM32F302xx/STM32F303xx

Electrical characteristics

Table 70. DAC characteristics (continued)

Symbol

Parameter

Min Typ

Max

Unit

Comments

Settling time (full scale: for a

10-bit input code transition

tSETTLING(3)

between the lowest

highest input codes

and the

when

-

3

DAC_OUT reaches final

value ±1LSB

Max frequency for a correct

Update DAC_OUT change when

rate(3) small variation in the input

-

-

code (from code i to i+1LSB)

Wakeup time from off state

tWAKEUP(3) (Setting the ENx bit in the

- 6.5

DAC Control register)

Power supply rejection ratio

PSRR+ (1) (to VDDA) (static DC

- –67

measurement

4

µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

1

MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

10

µs input code between lowest and

highest possible ones.

–40

dB No RLOAD, CLOAD = 50 pF

1. Guaranteed by design, not tested in production.

2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is

involved.

3. Data based on characterization results, not tested in production.

Figure 34. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC

Buffer(1)

12-bit

digital to

analog

converter

DACx_OUT

R LOAD

C LOAD

ai17157

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly

without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the

DAC_CR register.

Doc ID 023353 Rev 5

113/133

Share Link: