STM32F302XC 查看數據表（PDF） - STMicroelectronics

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STM32F302XC

ARM Cortex-M4F 32b MCU+FPU, up to 256KB Flash+48KB SRAM 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V operation

STMicroelectronics 

Electrical characteristics

STM32F302xx/STM32F303xx

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or

source up to +/- 20 mA (with a relaxed VOL/VOH).

In the user application, the number of I/O pins which can drive current must be limited to

respect the absolute maximum rating specified in Section 6.2:

● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run

consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating

IVDD(Σ) (see Table 20).

● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run

consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating

IVSS(Σ) (see Table 20).

Output voltage levels

Unless otherwise specified, the parameters given in Table 53 are derived from tests

performed under ambient temperature and VDD supply voltage conditions summarized in

Table 22. All I/Os (FT, TTa and Tc unless otherwise specified) are CMOS and TTL

compliant.

Table 53. Output voltage characteristics

Symbol

Parameter

Conditions

Min

Max Unit

VOL(1)

VOH(3)

VOL (1)

VOH (3)

VOL(1)(4)

VOH(3)(4)

VOL(1)(4)

VOH(3)(4)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port(2)

-

0.4

IIO = +8 mA

2.7 V < VDD < 3.6 V VDD–0.4

-

TTL port(2)

-

0.4

IIO =+ 8mA

2.7 V < VDD < 3.6 V

2.4

-

IIO = +20 mA

-

1.3

V

2.7 V < VDD < 3.6 V VDD–1.3

-

IIO = +6 mA

-

0.4

2 V < VDD < 2.7 V

VDD–0.4

-

VOLFM+(1)(4)

Output low level voltage for an FTf I/O pin in

FM+ mode

IIO = +20 mA

2.7 V < VDD < 3.6 V

-

0.4

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 20 and the sum of

IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 20 and the sum

of IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).

4. Data based on design simulation.

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Doc ID 023353 Rev 5

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