TC850CLW 查看數據表（PDF） - Microchip Technology
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TC850CLW Datasheet PDF : 26 Pages
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TC850
8.0 DIGITAL SECTION TYPICAL
APPLICATIONS
8.1 Oscillator
The TC850 may operate with a crystal oscillator. The
crystal selected should be designed for a Pierce
oscillator, such as an AT-cut quartz crystal. The crystal
oscillator schematic is shown in Figure 8-1.
Since low-frequency crystals are very large and
ceramic resonators are too lossy, the TC850 clock
should be derived from an external source, such as a
microprocessor clock. The clock should be input on the
OSC1 pin and no connection should be made to the
OSC2 pin. The external clock should swing between
DGND and VDD.
Since oscillator frequency is ÷ 4 internally and each
conversion requires 1280 internal clock cycles, the
conversion time will be:
EQUATION 8-1:
Conversion Time =
4 x 1280
FCLOCK
An important advantage of the integrating ADC is the
ability to reject periodic noise. This feature is most often
used to reject line frequency (50 Hz or 60 Hz) noise.
Noise rejection is accomplished by selecting the inte-
gration period equal to one or more line frequency
cycles. The desired clock frequency is selected as
follows:
EQUATION 8-2:
FCLOCK = FNOISE x 4 x 256
where:
FNOISE is the noise frequency to be rejected,
4 represents the clock divider,
256 is the number of integrate cycles.
For example, 60 Hz noise will be rejected with a clock
frequency of 61.44 kHz, giving a conversion rate of 12
conversions/sec. Integer submultiples of 61.44 kHz
(such as 30.72 kHz, etc.) will also reject 60 Hz noise.
For 50 Hz noise rejection, a 51.2 kHz frequency is
recommended.
If noise rejection is not important, other clock frequen-
cies can be used. The TC850 will typically operate at
conversion rates ranging from 3 to 40 conversions/sec,
corresponding to oscillator frequencies from 15.36 kHz
to 204.8 kHz.
DS21479C-page 16
10 MΩ
TC850
17 61.44 kHz
¸4
18
100 pF
100 pF
System
Clock
FIGURE 8-1:
Crystal Oscillator Schematic
8.2 Data Bus Interfacing
The TC850 provides an easy and flexible digital inter-
face. A 3-state data bus and six control inputs permit
the TC850 to be treated as a memory device, in most
applications. The conversion result can be accessed
over an 8-bit bus or via a μP I/O port.
A typical μP bus interface for the TC850 is shown in
Figure 8-2. In this example, the TC850 operates in the
Demand mode and conversion begins when a write
operation is performed to any decoded address space.
The BUSY output interrupts the μP at the end-of-con-
version.
The A/D conversion result is read as three memory
bytes. The two LSBs of the address bus select high/low
byte and overrange/polarity bit data, while high-order
address lines enable the CE input.
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
CE
L/H
OVR/POL
RD
WR
BUSY
CS
CONT/DEMAND
TC850
Address
Decode
+5V
DB0
DB1
DB2
DB3
DB4
DB5
DB6
μP
DB7
A2
A15
A0
A1
RD
WR
INTERRUPT
Address
X00
X01
X10
Data Bus
High Byte Polarity
Low Byte
High Byte Overrange
FIGURE 8-2:
Bus
Interface to Typical μP Data
© 2006 Microchip Technology Inc.
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