ST72F324K4TCRE 查看數據表（PDF） - STMicroelectronics

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ST72F324K4TCRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

Figure 53. Clearing the WCOL bit (Write Collision flag) software sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step Read SPICSR

2nd Step

Read SPIDR

Result

SPIF = 0

WCOL = 0

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

Read SPICSR

Result

Note: Writing to the SPIDR register

Product(s) - Obsolete Product(s) Note:

2nd Step

Read SPIDR

WCOL = 0

instead of reading it does not reset

the WCOL bit.

Single master systems

A typical single master system may be configured, using an MCU as the master and four

MCUs as slaves (see Figure 54).

The master device selects the individual slave devices by using four pins of a parallel port to

control the four SS pins of the slave devices.

The SS pins are pulled high during reset since the master device ports will be forced to be

inputs at that time, thus disabling the slave devices.

To prevent a bus conflict on the MISO line the master allows only one active slave device

during a transmission.

For more security, the slave device may respond to the master with the received data byte.

Then the master will receive the previous byte back from the slave device if all MISO and

MOSI pins are connected and the slave has not written to its SPIDR register.

Other transmission security methods can use ports for handshake lines or data bytes with

command fields.

Figure 54. Single master/multiple slave configuration

Obsolete SCK

SS

Slave

MCU

SCK

SS

Slave

MCU

SCK

SS

Slave

MCU

SCK

SS

Slave

MCU

MOSI MISO

MOSI MISO

MOSI MISO

MOSI MISO

MOSI MISO

SCK

Master

MCU

5V

SS

Doc ID 13841 Rev 1

105/193

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