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ST72F324J2TCRS 查看數據表(PDF) - STMicroelectronics

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ST72F324J2TCRS Datasheet PDF : 194 Pages
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ST72324xx-Auto
11 Instruction set
Instruction set
11.1 CPU addressing modes
The CPU features 17 different addressing modes which can be classified in 7 main groups
(see Table 75).
:
Table 75. Addressing mode groups
Group
Example
Inherent
nop
Immediate
t(s) Direct
Indexed
uc Indirect
rod Relative
P Bit operation
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
bset byte,#5
lete The CPU Instruction Set is designed to minimize the number of bytes required per
o instruction: To do so, most of the addressing modes may be divided in two submodes called
s long and short:
Ob Long addressing mode is more powerful because it can use the full 64 Kbyte address
- space, however it uses more bytes and more CPU cycles.
) Short addressing mode is less powerful because it can generally only access page
t(s zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
c memory to memory instructions use short addressing modes only (CLR, CPL, NEG,
u BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP).
rod The ST7 Assembler optimizes the use of long and short addressing modes.
P Table 76. CPU addressing mode overview
leteMode
Syntax
so Inherent
ObImmediate
nop
ld A,#$55
Destination Pointer address Pointer size Length
(Hex.)
(Hex.) (bytes)
+0
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No offset Direct Indexed ld A,(X)
00..FF
+0
Short
Direct Indexed ld A,($10,X)
00..1FE
+1
Long
Direct Indexed ld A,($1000,X)
0000..FFFF
+2
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
Short
Indirect Indexed ld A,([$10],X)
00..1FE
00..FF
byte
+2
Doc ID 13841 Rev 1
137/193

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