ST72F324J2TCRS 查看數據表（PDF） - STMicroelectronics

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ST72F324J2TCRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

Device configuration and ordering information

Table 116. Option byte 0 bit description (continued)

Bit

Name

Function

Voltage detection

These option bits enable the voltage detection block (LVD and AVD)

with a selected threshold for the LVD and AVD.

OPT4:3

VD[1:0]

00: Selected LVD = Highest threshold (VDD~4V).

01: Selected LVD = Medium threshold (VDD~3.5V).

10: Selected LVD = Lowest threshold (VDD~3V).

11: LVD and AVD off

Caution: If the medium or low thresholds are selected, the detection

may occur outside the specified operating voltage range. Below 3.8V,

device operation is not guaranteed. For details on the AVD and LVD

) OPT2:1

solete Product(s OPT0

-

FMP_R

threshold levels refer to Section 12.4.1 on page 150.

Reserved, must be kept at default value

Flash memory readout protection

Readout protection, when selected, provides a protection against

program memory content extraction and against write access to Flash

memory.

Erasing the option bytes when the FMP_R option is selected causes

the whole user memory to be erased first, afterwhich the device can

be reprogrammed. Refer to Section 4.3.1 on page 24 and the ST7

Flash Programming Reference Manual for more details.

0: Readout protection enabled

1: Readout protection disabled

- Ob Table 117. Option byte 1 bit description

t(s) Bit

Name

Function

Produc OPT7

PKG1

Pin package selection bit

This option bit selects the package (see Table 118).

Note: On the chip, each I/O port has eight pads. Pads that are not

bonded to external pins are in input pull-up configuration after reset.

The configuration of these pads must be kept at reset state to avoid

added current consumption.

ObsoleteOPT6

RSTC

Reset clock cycle selection

This option bit selects the number of CPU cycles applied during the

reset phase and when exiting Halt mode. For resonator oscillators, it

is advised to select 4096 due to the long crystal stabilization time.

0: Reset phase with 4096 CPU cycles

1: Reset phase with 256 CPU cycles

OPT5:4

OSCTYPE[1:0]

Oscillator type

These option bits select the ST7 main clock source type.

00: Clock source = Resonator oscillator

01: Reserved

10: Clock source = Internal RC oscillator

11: Clock source = External source

Doc ID 13841 Rev 1

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