ST72F324J2TARS 查看數據表（PDF） - STMicroelectronics

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ST72F324J2TARS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

Supply, reset and clock management

The interrupt on the rising edge is used to inform the application that the VDD warning state

is over.

If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay

selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.

If trv is greater than 256 or 4096 cycles then:

● If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then two AVD

interrupts will be received: the first when the AVDIE bit is set, and the second when the

threshold is reached.

● If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached, then only one

AVD interrupt will occur.

Figure 15. Using the AVD to monitor VDD

t(s) VDD

duc VIT+(AVD)

ro VIT-(AVD)

P VIT+(LVD)

te VIT-(LVD)

Early warning interrupt

(power has dropped, MCU not

not yet in reset)

Vhyst

trv Voltage rise time

bsole AVDF bit

0

- O AVD Interrupt

Request

) if AVDIE bit = 1

ct(s LVD RESET

1

Reset value

Interrupt process

1

0

Interrupt process

Obsolete Produ 6.5.3

Low power modes

Table 10.

Mode

Wait

Effect of low power modes on SI

Description

No effect on SI. AVD interrupt causes the device to exit from Wait mode.

Halt The CRSR register is frozen.

6.5.4

Interrupts

The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask

in the CC register is reset (RIM instruction).

M

Table 11. AVD interrupt control/wake-up capability

Interrupt event

Event flag Enable Control bit Exit from WAIT Exit from HALT

AVD event

AVDF

AVDIE

Yes

No

Doc ID 13841 Rev 1

39/193

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