ST72F324J2TCRE 查看數據表（PDF） - STMicroelectronics

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ST72F324J2TCRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

10.1.5 Low power modes

Table 34. Effect of lower power modes on Watchdog

Mode

Description

Slow

No effect on Watchdog

Wait

OIE bit in WDGHALT bit in

MCCSR register option byte

No Watchdog reset is generated. The MCU enters

Halt mode. The Watchdog counter is decremented

t(s) 0

roduc Halt

te P 0

t(s) - Obsole 1

once and then stops counting and is no longer able to

generate a watchdog reset until the MCU receives an

external interrupt or a reset.

0

If an external interrupt is received, the Watchdog

restarts counting after 256 or 4096 CPU clocks. If a

reset is generated, the Watchdog is disabled (reset

state) unless Hardware Watchdog is selected by

option byte. For application recommendations, see

Section 10.1.7 below.

1

A reset is generated.

No reset is generated. The MCU enters Active Halt

mode. The Watchdog counter is not decremented. It

stop counting. When the MCU receives an oscillator

x

interrupt or external interrupt, the Watchdog restarts

counting immediately. When the MCU receives a

reset the Watchdog restarts counting after 256 or

4096 CPU clocks.

uc 10.1.6

Obsolete Prod 10.1.7

Hardware Watchdog option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the

WDGA bit in the WDGCR is not used. Refer to the option byte description in Section 14.1:

Flash device configuration on page 178.

Using Halt mode with the WDG (WDGHALT option)

The following recommendation applies if Halt mode is used when the watchdog is enabled:

Before executing the HALT instruction, refresh the WDG counter to avoid an unexpected

WDG reset immediately after waking up the microcontroller.

10.1.8

Interrupts

None.

Doc ID 13841 Rev 1

69/193

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