ST72F324K4TCRE 查看數據表（PDF） - STMicroelectronics

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ST72F324K4TCRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

Table 50. CR2 register description (continued)

Bit Name

Function

Output Compare 2 Pin Enable

6 OC2E

This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in

Output Compare mode). Whatever the value of the OC2E bit, the Output Compare

2 function of the timer remains active.

0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

One Pulse Mode

5 OPM

0: One Pulse mode is not active.

1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the

OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the

generated pulse depends on the contents of the OC1R register.

t(s) Pulse Width Modulation

duc 4 PWM

0: PWM mode is not active.

1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the

length of the pulse depends on the value of OC1R register; the period depends on

ro the value of OC2R register.

P Clock Control

bsolete 3:2 CC[1:0]

The timer clock mode depends on these bits.

00: Timer clock = fCPU/4

01: Timer clock = fCPU/2

10: Timer clock = fCPU/8

11: Timer clock = external clock (where available)

Note: If the external clock pin is not available, programming the external clock

O configuration stops the counter.

) - Input Edge 2

duct(s 1 IEDG2

This bit determines which type of level transition on the ICAP2 pin will trigger the

capture.

0: A falling edge triggers the capture.

1: A rising edge triggers the capture.

roExternal Clock Edge

lete P 0 EXEDG

This bit determines which type of level transition on the external clock pin EXTCLK

will trigger the counter register.

0: A falling edge triggers the counter register.

1: A rising edge triggers the counter register.

Obso Control/Status Register (CSR)

CSR

7

6

5

ICF1

OCF1

TOF

RO

RO

RO

4

ICF2

RO

3

OCF2

RO

Reset value: xxxx x0xx (xxh)

2

1

0

TIMD

Reserved

R/W

-

92/193

Doc ID 13841 Rev 1

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