UPSD3213B-40U1F(2009) 查看數據表（PDF） - STMicroelectronics

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UPSD3213B-40U1F
(Rev.:2009)

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

Watchdog timer

10 Watchdog timer

UPSD3212A, UPSD3212C, UPSD3212CV

The hardware watchdog timer (WDT) resets the UPSD321xx devices when it overflows. The

WDT is intended as a recovery method in situations where the CPU may be subjected to a

software upset. To prevent a system reset the timer must be reloaded in time by the

application software. If the processor suffers a hardware/software malfunction, the software

will fail to reload the timer. This failure will result in a reset upon overflow thus preventing the

processor running out of control.

In the Idle mode the watchdog timer and reset circuitry remain active. The WDT consists of

a 22-bit counter, the Watchdog Timer RESET (WDRST) SFR and Watchdog Key Register

(WDKEY).

Since the WDT is automatically enabled while the processor is running. the user only needs

to be concerned with servicing it.

The 22-bit counter overflows when it reaches 4194304 (3FFFFFH). The WDT increments

once every machine cycle.

This means the user must reset the WDT at least every 4194304 machine cycles (1.258

seconds at 40MHz). To reset the WDT the user must write a value between 00-7EH to the

WDRST register. The value that is written to the WDRST is loaded to the 7MSB of the 22-bit

counter. This allows the user to pre-loaded the counter to an initial value to generate a

flexible Watchdog time out period. Writing a “00” to WDRST clears the counter.

The watchdog timer is controlled by the watchdog key register, WDKEY. Only pattern

01010101 (=55H), disables the watchdog timer. The rest of pattern combinations will keep

the watchdog timer enabled. This security key will prevent the watchdog timer from being

terminated abnormally when the function of the watchdog timer is needed.

In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the

processor while in Idle, the user should always set up a timer that will periodically exit Idle,

service the WDT, and re-enter Idle mode.

Watchdog reset pulse width depends on the clock frequency. The reset period is tfOSC x 12

x 222.

The RESET pulse width is tfOSC x 12 x 215.

Table 32.

7

WDKEY7

Watchdog timer key register (WDKEY: 0AEh)

6

5

4

3

2

WDKEY6 WDKEY5 WDKEY4 WDKEY3 WDKEY2

1

WDKEY1

0

WDKEY0

Table 33.

Bit

7 to 0

Description of the WDKEY Bits

Symbol

Function

WDKEY7 Enable or disable watchdog timer.

to

WDKEY0 01010101 (=55h): disable watchdog timer. Others: enable watchdog timer

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