CS2300CP-CZZR 查看數據表（PDF） - Cirrus Logic

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CS2300CP-CZZR

Fractional-N Clock Multiplier with Internal LCO

Cirrus Logic 

8.2.3

PLL Clock Output Disable (ClkOutDis)

This bit controls the output driver for the CLK_OUT pin.

ClkOutDis

0

1

Application:

Output Driver State

CLK_OUT output driver enabled.

CLK_OUT output driver set to high-impedance.

“PLL Clock Output” on page 19

CS2300-CP

8.3 Device Configuration 1 (Address 03h)

7

RModSel2

6

RModSel1

5

RModSel0

4

Reserved

3

Reserved

2

1

0

AuxOutSrc1 AuxOutSrc0 EnDevCfg1

8.3.1

R-Mod Selection (RModSel[2:0])

Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N.

RModSel[2:0]

000

001

010

011

100

101

110

111

Application:

R-Mod Selection

Left-shift R-value by 0 (x 1).

Left-shift R-value by 1 (x 2).

Left-shift R-value by 2 (x 4).

Left-shift R-value by 3 (x 8).

Right-shift R-value by 1 (÷ 2).

Right-shift R-value by 2 (÷ 4).

Right-shift R-value by 3 (÷ 8).

Right-shift R-value by 4 (÷ 16).

“Ratio Modifier (R-Mod)” on page 17

8.3.2

Auxiliary Output Source Selection (AuxOutSrc[1:0])

Selects the source of the AUX_OUT signal.

AuxOutSrc[1:0]

00

01

10

11

Application:

Auxiliary Output Source

Reserved.

CLK_IN.

CLK_OUT.

PLL Lock Status Indicator.

“Auxiliary Output” on page 19

Note: When set to 11, AuxLckCfg sets the polarity and driver type. See “AUX PLL Lock Output Config-

uration (AuxLockCfg)” on page 27.

DS843F1

25

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