CDB8952T-IQ 查看數據表（PDF） - Cirrus Logic
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CDB8952T-IQ Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Loopback, Bypass, and Receiver Error Mask Register - Address 18h (Cont.)
BIT
NAME
TYPE
3
Premature End
Read/Write 0
Error Report Select
RESET
DESCRIPTION
When set, this bit causes premature end errors to be
reported by a value of 4h on RXD[3:0] and the asser-
tion of RX_ER.
When clear, this bit causes premature end errors to
be reported by a value of 6h on RXD[3:0] and the
assertion of RX_ER.
2
Link Error Report Read/Write 0
Enable
1
Packet Error Report Read/Write 0
Enable
0
Code Error Report Read/Write 0
Enable
A premature end error is caused by the detection of
two IDLE symbols in the 100 Mb/s receive data
stream prior to the End of Stream Delimiter.
When set, this bit causes link errors to be reported by
a value of 3h on RXD[3:0] and the assertion of
RX_ER. When clear, link errors are not reported
across the MII.
When set, this bit causes packet errors to be reported
by a value of 2h on RXD[3:0] and the assertion of
RX_ER. When clear, packet errors are not reported
across the MII.
When set, code errors are reported and transmitted
on RXD[3:0].
When clear, this bit enables the Code Error Report
values on RXD[3:0] as selected by the Code Error
Report Select bit and also causes the assertion of
TX_ER to transmit a HALT code group.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS206TPP2
57
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