C8051F521A-IM 查看數據表（PDF） - Silicon Laboratories
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C8051F521A-IM Datasheet PDF : 221 Pages
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C8051F52x/F53x
Table 16.1. SPI Slave Timing Parameters
Parameter
Description
Min
Master Mode Timing* (See Figure 16.6 and Figure 16.7)
TMCKH
TMCKL
TMIS
TMIH
SCK High Time
SCK Low Time
MISO Valid to SCK Sample Edge
SCK Sample Edge to MISO Change
1 x TSYSCLK
1 x TSYSCLK
20
0
Slave Mode Timing* (See Figure 16.8 and Figure 16.9)
TSE
TSD
TSEZ
TSDZ
TCKH
TCKL
TSIS
TSIH
TSOH
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
2 x TSYSCLK
2 x TSYSCLK
—
—
5 x TSYSCLK
5 x TSYSCLK
2 x TSYSCLK
2 x TSYSCLK
—
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK) in ns.
The maximum possible frequency of the SPI can be calculated as:
Transmission: SYSCLK/2
Reception: SYSCLK/10
Max
Units
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
4 x TSYSCLK ns
4 x TSYSCLK ns
—
ns
—
ns
—
ns
—
ns
4 x TSYSCLK ns
Rev. 1.4
163
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