C8051F521A-IM 查看數據表（PDF） - Silicon Laboratories

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C8051F521A-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

18.2.2. 8-bit Timers with Auto-Reload

When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-

ate in auto-reload mode as shown in Figure 18.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH

holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is

always running when configured for 8-bit Mode.

Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock

source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or

the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:

T2MH

0

0

1

T2XCLK

0

1

X

TMR2H Clock Source

SYSCLK / 12

External Clock / 8

SYSCLK

T2ML

0

0

1

T2XCLK

0

1

X

TMR2L Clock Source

SYSCLK / 12

External Clock / 8

SYSCLK

The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows

from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time

TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-

ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the

TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags

are not cleared by hardware and must be manually cleared by software.

T2XCLK

SYSCLK / 12

0

External Clock / 8

1

CKCON

TTTTTTSS

3 3 2 2 1 0CC

MMMMMMA A

HLHL

10

0

TR2

1

SYSCLK

TMR2RLH Reload

TCLK

TMR2H

TMR2RLL Reload

TF2H

TF2L

TF2LEN

T2SPLIT

TR2

T2XCLK

Interrupt

1

TCLK TMR2L

0

Figure 18.5. Timer 2 8-Bit Mode Block Diagram

Rev. 1.4

191

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