C8051F521A-IM 查看數據表（PDF） - Silicon Laboratories

零件编号

产品描述 (功能)

生产厂家

C8051F521A-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

SFR Definition 4.9. ADC0TK: ADC0 Tracking Mode Select

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

AD0PWR

AD0TM

AD0TK

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0 SFR Address:

(bit addressable) 0xBA

Bits7–4: AD0PWR3–0: ADC0 Burst Power-Up Time.

For BURSTEN = 0:

ADC0 power state controlled by AD0EN.

For BURSTEN = 1 and AD0EN = 1;

ADC0 remains enabled and does not enter the very low power state.

For BURSTEN = 1 and AD0EN = 0:

ADC0 enters the very low power state as specified in Table 2.3 on page 28 and is enabled

after each convert start signal. The Power Up time is programmed according to the following

equation:

AD0PWR = T----s---t--a---r---t--u---p-- – 1 or Tstartup = AD0PWR + 1200ns

200ns

Bits3–2: AD0TM1–0: ADC0 Tracking Mode Select Bits.

00: Reserved.

01: ADC0 is configured to Post-Tracking Mode.

10: ADC0 is configured to Pre-Tracking Mode.

11: ADC0 is configured to Dual-Tracking Mode (default).

Bits1–0: AD0TK1–0: ADC0 Post-Track Time.

Post-Tracking time is controlled by AD0TK as follows:

00: Post-Tracking time is equal to 2 SAR clock cycles + 2 FCLK cycles.

01: Post-Tracking time is equal to 4 SAR clock cycles + 2 FCLK cycles.

10: Post-Tracking time is equal to 8 SAR clock cycles + 2 FCLK cycles.

11: Post-Tracking time is equal to 16 SAR clock cycles + 2 FCLK cycles.

68

Rev. 1.4

Share Link: