ST6246 查看數據表（PDF） - STMicroelectronics
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ST6246 Datasheet PDF : 72 Pages
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ST62T46B/E46B
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
7
0
- LES ESB GEN -
-
-
-
Bit 7, Bits 3-0 = Unused.
3.4.4 Interrupt Sources
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
Interrupt sources available on the with associated mask bit to enable/disable the in-
ST62E46B/T40B are summarized in the Table 9 terrupt request.
Table 9. Interrupt Requests and Mask Bits
Peripheral
Register
GENERAL
TIMER 1
TIMER 2
A/D CONVERTER
SPI
Port PAn
Port PBn
Port PCn
PSS
32kHz OSC
IOR
TSCR1
TSCR2
ADCR
SPI
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
PSSCR
32OCR
Address
Register
C8h
D4h
D7h
D1h
C2h
C0h-C4h
C1h-C5h
C6h-CFh
DAh
DBh
Mask bit
GEN
Masked Interrupt Source
Interrupt
source
All Interrupts, excluding NMI All
ETI
TMZ: TIMER Overflow
source 3
EAI
ALL
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn
PEI
EOSCI
EOC: End of Conversion
End of Transmission
PAn pin
PBn pin
PCn pin
PIF:
OSCEOC
source 4
source 1
source 2
source 2
source 2
source 0
source 3
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