QL82SD-6PS484M 查看數據表（PDF） - QuickLogic Corporation
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QL82SD-6PS484M Datasheet PDF : 60 Pages
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QL82SD Device Data Sheet Rev C
SERDES Switching Characteristics - Serializer/Transmitter]
Symbol
tHZD
tLZD
tZHD
tZLD
tDIS
tDIH
tPLD
Symbol
tHZD
tLZD
tZHD
tZLD
tDIS
tDIH
tSD
tSCP
tTXD[N-1]
tPLD
tHZD
tLZD
tZHD
tZLD
tASD
tASC
Table 16: Serializer/Transmitter Switching Characteristics
CDR (10:1) Mode
Parameter
Conditions
Min
Typ
Max
Units
pad_ChX_p/n High to Tri-State Delay
1.9
2.2
2.5
nS
pad_ChX_p/n Low to Tri-State Delay
1.9
2.0
2.2
nS
Figure 18
pad_ChX_p/n Tri-State to High Delay
1.9
2.4
3.0
nS
pad_ChX_p/n Tri-State to Low Delay
2.0
2.3
2.8
nS
ChX_txd[9:0] Setup to ChX_txclk
2.6
Figure 19
ChX_txd[9:0] Hold from ChX_txclk
2.1
3.2
nS
2.7
nS
Serializer PLL Lock Time
Figure 20
90
uS
Channel Link (8:1, 7:1, 4:1) Mode
Parameter
Conditions
Min
Typ
Max
Units
pad_ChX_p/n High to Tri-State Delay
1.9
2.2
2.5
nS
pad_ChX_p/n Low to Tri-State Delay
1.9
2.0
2.2
nS
Figure 18
pad_ChX_p/n Tri-State to High Delay
1.9
2.4
3.0
nS
pad_ChX_p/n Tri-State to Low Delay
2.0
2.3
2.8
nS
ChX_txd[N-1:0] Setup to ChX_txclk
2.6
3.2
nS
ChX_txd[N-1:0] Hold from ChX_txclk
2.1
2.7
nS
Serializer Delay
Serial Transmit Clock Period
Figure 21
1.7
nS
T/mode
nS
Transmitter Output Pulse Position for
Bit [N-1]
[N-1] x tSCP + 1.1
[N-1] x tSCP + 1.5 nS
Serializer PLL Lock Time
Figure 20
90
uS
Asynchronous Level Conversion (1:1) Mode
pad_ChX_p/n High to Tri-State Delay
1.9
2.2
2.5
nS
pad_ChX_p/n Low to Tri-State Delay
1.9
2.0
2.2
nS
Figure 18
pad_ChX_p/n Tri-State to High Delay
1.9
2.4
3.0
nS
pad_ChX_p/n Tri-State to Low Delay
2.0
2.3
2.8
nS
Asynchronous Serializer Delay -
Data Channel
Asynchronous Serializer Delay -
Channel Clock
Figure 22
1.8
nS
1.7
nS
© 2002 QuickLogic Corporation
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