MSP3400CPP 查看數據表（PDF） - Micronas

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MSP3400CPP

Multistandard Sound Processor

Micronas 

MSP 3400C

PRELIMINARY DATA SHEET

MSP Clock Output

Clock Inverter Output

typ. 20 ns

at inverter output

Timing window

for the low to high edge at

pin 17 of DMA 2381 (XTAL2)

< 42 ns

> 10 ns

Fig. 10–2: Timing requirements for the clock signal at the DMA 2381 clock input

In the following table, the input/output clock-specification of the D2MAC circuit is shown.

Table 10–1: Clock input and output specification for MSPs

XTAL_IN min

(minimum amplitude)

C input

(after Reset)

AUD_CL_OUT min

with C load

Rout (HF) typ.

MSP 3400C >C6

new Version

> 0.7 Vpp

22 pF

> 1.2 Vpp

40 pF

150 Ω

MSP 3410/00 TC27

new Version

> 0.7 Vpp

22 pF

> 1.2 Vpp

40 pF

120 Ω

MSP 3410/00 TC15

actual Version

> 0.7 Vpp

31 pF

> 1.0 Vpp

43 pF

120 Ω

Table 10–2: Clock input and output specification for ICs connected to MSP

XTAL_IN min

Clock-in min

(minimal amplitude)

C input

DMA 2381

> 0.7 Vpp

24 pF

10 pF with: Adr.

204,14=1

DMA 2386

> 0.7 Vpp

7pF

AMU2481

> 0.7 Vpp

7pF

For the DMA_SYNC input specification of the MSP, please refer to page 54 “VDMAIL, VDMAIH.”

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