CS4353(2009) 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CS4353
(Rev.:2009)

3.3 V Stereo Audio DAC with 2 VRMS Line Output

Cirrus Logic 

CS4353

4.4 Digital Interface Format

The device will accept audio samples in either I²S or Left-Justified digital interface formats, as illustrated in

Table 6.

The desired format is selected via the I²S/LJ pin. For an illustration of the required relationship between the

LRCK, SCLK and SDIN, see Figures 5-6. For all formats, SDIN is valid on the rising edge of SCLK. Also,

SCLK must have at least 32 cycles per LRCK period in the Left-Justified format.

For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-

nel Serial Audio Interface: A Tutorial, available at http://www.cirrus.com.

I²S/LJ

Description

0 I²S, up to 24-bit Data

1 Left-Justified, up to 24-bit Data

Table 6. Digital Interface Format

Figure

5

6

LRCK

SCLK

SDIN

Left Channel

Right Channel

MSB -1 -2 -3 -4 -5

+5 +4 +3 +2 +1 LSB

MSB -1 -2 -3 -4

+5 +4 +3 +2 +1 LSB

Figure 5. I²S, up to 24-bit Data

LRCK

SCLK

Left Channel

Right Channel

SDIN

MSB -1 -2 -3 -4 -5

+5 +4 +3 +2 +1 LSB

MSB -1 -2 -3 -4

+5 +4 +3 +2 +1 LSB

Figure 6. Left-justified up to 24-bit Data

4.5 Internal High-Pass Filter

The device includes an internal digital high-pass filter. This filter prevents a constant digital offset from cre-

ating a DC voltage on the analog output pins. The filter’s corner frequency is well below the audio band; see

the Combined Interpolation & On-Chip Analog Filter Response table for filter specifications.

DS803F1

15

Share Link: