ATMEGA161-8PC 查看數據表（PDF） - Atmel Corporation

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ATMEGA161-8PC

8-bit Microcontroller with 16K Bytes In-System Programmable Flash

Atmel Corporation 

The TXENn bit in UCSRnB enables the UART transmitter when set (one). When this bit is cleared (zero), the PD1 (UART0)

or PB3 (UART1) pin can be used for general I/O. When TXENn is set, the UART Transmitter will be connected to PD1

(UART0) or PB3 (UART1), which is forced to be an output pin regardless of the setting of the DDD1 bit in DDRD (UART0)

or DDB3 in DDRB (UART1). Note that PB3 (UART1) also is used as one of the input pins to the Analog Comparator. It is

therefore not recommended to use UART1 if the Analog Comparator also is used in the application at the same time.

Data Reception

Figure 46 shows a block diagram of the UART Receiver

Figure 46. UART Receiver

DATA BUS

XTAL

BAUD RATE

GENERATOR

PIN CONTROL

LOGIC

BAUD x 16

/16

BAUD

STORE UDRn

PD0/

PB2

RXDn DATA RECOVERY

LOGIC

UART I/O DATA

REGISTER (UDRn)

10(11)-BIT RX

SHIFT REGISTER

UART CONTROL AND

STATUS REGISTER

(UCSRnB)

UART CONTROL AND

STATUS REGISTER

(UCSRnA)

DATA BUS

n = 0,1

RXCn

IRQ

The receiver front-end logic samples the signal on the RXDn pin at a frequency 16 times the baud rate. While the line is

idle, one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection

sequence is initiated. Let sample 1 denote the first zero-sample. Following the 1 to 0-transition, the receiver samples the

RXDn pin at samples 8, 9 and 10. If two or more of these three samples are found to be logical ones, the start bit is rejected

as a noise spike and the receiver starts looking for the next 1 to 0-transition.

If however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also

sampled at samples 8, 9 and 10. The logical value found in at least two of the three samples is taken as the bit value. All

bits are shifted into the transmitter shift register as they are sampled. Sampling of an incoming character is shown in Figure

47. Note that the description above is not valid when the UART transmission speed is doubled. See “Double Speed Trans-

mission” on page 68 for a detailed description.

62

ATmega161(L)

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