USB97CFDC2-01 查看數據表（PDF） - SMSC -> Microchip
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USB97CFDC2-01 Datasheet PDF : 24 Pages
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nDIR
nSTEP
nDS0
nINDEX
nRDATA
nWDATA
t3
t4
t1
t2
t5
t6
t7
t8
NAME
PARAMETER
MIN
t1
nDIR Set Up to nSTEP Low
t2
nSTEP Active Time Low
t3
nDIR Hold Time After nSTEP
t4
nSTEP Cycle Time
t5
nDS0-1 Hold Time from nSTEP Low
t6
nINDEX Pulse Width
t7
nRDATA Active Time Low
t8
nWDATA Write Data Width Low
*X specifies one MCLK period and Y specifies one WCLK period.
MCLK = 16x Data Rate (at 500 Kbp/s MCLK = 8 MHz)
WCLK = 2x Data Rate (at 500 Kbp/s WCLK = 1 MHz)
TYP MAX
4
24
96
132
20
2
40
.5
UNITS
X*
X*
X*
X*
X*
X*
ns
Y*
FIGURE 3 - DISK DRIVE TIMING
SMSC DS – USB97CFDC2-01
Page 18
DATASHEET
Rev. 02-27-07
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