ADV7403BSTZ-110(RevSpA) 查看數據表（PDF） - Analog Devices

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ADV7403BSTZ-110
(Rev.:RevSpA)

12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer

Analog Devices 

ADV7403

TIMING DIAGRAMS

t3

SDA1/SDA2

t5

t3

SCLK1/SCLK2

t6

t1

t2

t7

t4

t8

Figure 3. I2C Timing

LLC1

t9

t10

P0–P29, VS, HS,

FIELD/DE,

SFL/SYNC_OUT

t11

t12

Figure 4. Pixel Port and Control SDR Output Timing (SD Core)

LLC1

t9

t10

t13

t14

P0–P29, VS,

HS, FIELD/DE

Figure 5. Pixel Port and Control SDR Output Timing (CP Core)

LLC1

P6–P9,

P10–P19

t16

t15

t18

t17

Figure 6. Pixel Port and Control DDR Output Timing (CP Core)

DCLK_IN

CONTROL

INPUTS

HS_IN

VS_IN

DE_IN

P0–P1, P10–P11,

P20–P21, P22–P29,

P31–P32, P33–P40

t20

t9 t10

t19

Figure 7. Digital Input Port and Control Input Timing

Rev. SpA | Page 12 of 24

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