ST72325J4B5 查看數據表（PDF） - STMicroelectronics

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ST72325J4B5

8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE

STMicroelectronics 

ST72325

12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage 1)

0.3xVDD

V

VIH Input high level voltage 1)

0.7xVDD

Vhys Schmitt trigger voltage hysteresis 2)

VOL Output low level voltage 3)

VDD=5V IIO=+2mA

2.5

V

0.2

0.5

IIO Input current on RESET pin

2

mA

RON Weak pull-up equivalent resistor

20

30

120

kΩ

tw(RSTL)out Generated reset pulse duration

Stretch applied on

external pulse

0

Internal reset sources

20

426)

µs

30

426)

µs

th(RSTL)in External reset pulse hold time 4)

tg(RSTL)in Filtered glitch duration 5)

2.5

µs

200

ns

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

the RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-

vironments.

6. Data guaranteed by design, not tested in production.

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