ST72361xx-Auto
Electrical characteristics
Figure 116. SPI slave timing diagram with CPHA = 0
SS INPUT
tsu(SS)
tc(SCK)
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO)
th(SO)
MISO OUTPUT
See note 2
tsu(SI)
MSB OUT
th(SI)
BIT6 OUT
th(SS)
tr(SCK)
tf(SCK)
LSB OUT
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
tdis(SO)
See
note 2
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
Figure 117. SPI slave timing diagram with CPHA = 1
SS INPUT
tsu(SS)
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
ta(SO)
tw(SCKH)
tw(SCKL)
MISO OUTPUT
See
note 2
Hz
tsu(SI)
tc(SCK)
tv(SO)
MSB OUT
th(SI)
BIT6 OUT
th(SS)
th(SO)
tr(SCK)
tf(SCK)
LSB OUT
tdis(SO)
See
note 2
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration.
Doc ID 12468 Rev 3
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