STM32WB55RGQ7TR 查看數據表（PDF） - STMicroelectronics

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STM32WB55RGQ7TR

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5 and 802.15.4 radio solution

STMicroelectronics 

Memory mapping

5

Memory mapping

STM32WB55xx STM32WB35xx

The STM32WB55xx and STM32WB35xx devices feature a single physical address space

that can be accessed by the application processor and by the RF subsystem.

A part of the Flash memory and of the SRAM2a and SRAM2b memories are made secure,

exclusively accessible by the CPU2, protected against execution, read and write from CPU1

and DMA.

In case of shared resources the SW should implement arbitration mechanism to avoid

access conflicts. This happens for peripherals Reset and Clock Controller (RCC), Power

Controller (PWC), EXTI and Flash interface, and can be implemented using the built-in

semaphore block (HSEM).

By default the RF subsystem and CPU2 operate in secure mode. This implies that part of

the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and by

the CPU2. In this case the Host processor (CPU1) has no access to these resources.

The detailed memory map and the peripheral mapping can be found in the reference

manual RM0434.

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DS11929 Rev 10

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