STLC5464 查看數據表（PDF） - STMicroelectronics

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STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

III - FUNCTIONAL DESCRIPTION (continued)

Figure 3 : Unidirectional and Bidirectional Connections

OTSy, OTDMq

DOWN STREAM

DATA

MEMORY

n x 64kb/s

ITSx,ITDMp

DOWN STREAM

Unidirectional Connection

STLC5464

OTSy, OTDMq

DOWN STREAM

DATA

MEMORY

n x 64kb/s

ITSx,ITDMp

DOWN STREAM

ITSy, ITDMq

UP STREAM

DATA

MEMORY

n x 64kb/s

OTSx, OTDMp

UP STREAM

Bidirectional Connection

p, q = 0 to 7

x, y = 0 to 31

Figure 4 : Loop Back

OTSy, OTDMq

DOWN STREAM

OTSV

DATA

MEMORY

n x 64kb/s

ITSx,ITDMp

DOWN STREAM

ITSy, ITDMq

DATA

MEMORY

OTSx, OTDMp

n x 64kb/s

UP STREAM

UP STREAM

Loop

p, q = 0 to 7

Loopback per channel relevant if bidirectional connection has been done.

x, y = 0 to 31

III.1.5 - Delay through the Matrix

III.1.5.1 - Variable Delay Mode

In the variable delay mode, the delay through the

matrix dependson the relative positionsof the input

and output time slots in the frame.

So, some limits are fixed :

- the maximum delay is a frame + 2 time slots,

- the minimum delay is programmable.

Three time slots if IMTD = 1, in this case n = 2 in

the formula hereafter or two time slots if

IMTD = 0, in this case n = 1 in the same formula

(see Paragraph ”Switching Matrix Configuration

Reg SMCR (0C)H” on Page 60).

All the possibilities can be ranked in three cases :

a) If OTSy > ITSx + n then the variable delay is :

OTSy - ITSx Time slots

b) If ITSx < OTSy < ITSx + n then the variable delay

is :

OTSy - ITSx + 32 Time slots

c) OTSy < ITSx then the variable delay is :

32 - (ITSx - OTSy) Time slots.

N.B. Rule b) and rule c) are identical.

For n = 1 and n = 2, see Figure 5 on Page 18.

III.1.5.2 - Sequence Integrity Mode

In the sequence integrity mode (SI = 1, bit located

in the Connection Memory), the input time slots are

put out 2 frames later (see Figure 6 on Page 19).

In this case, the delay is definedby a singleexpres-

sion :

Constant Delay = (32 - ITSx) + 32 + OTSy

So, the delay in sequence integrity mode varies

from 33 to 95 time slots.

17/83

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