STLC5464 查看數據表（PDF） - STMicroelectronics
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STLC5464 Datasheet PDF : 83 Pages
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STLC5464
V - CLOCK TIMING (continued)
V.3 - GCI Interface
Figure 29 : GCI Synchro Signal delivered by the Multi-HDLC
125 µs
FS re ce ived by
the Multi-HDLC
CH0
CH1
CH7
DIN4/5
DO U T4/5
GCI Channel
B1
B2
MON D C/I AE
DCLK de livered by
the Multi-HDLC
FS CG de livered by
the Multi-HDLC
DOUT0/7, CB
if FSCG is connected to FS
DIN0/8
t1
t3
t3
t6
Bit 0, Time S lot 0
t7
t7
The four Multiplex Configura tion Registers a re a t ze ro (no de lay betwee n FS and Multiplexes ).
Symbol
t1
t3
t5
t6
t7
t7
Parameter
Clock Period if 4096kHz
Clock Period if 2048kHz
DCLK to FSCG
Duration FS
DCLK to Data 50pF
DCLK to Data 100pF
Set-up Time Data/DCLK
Hold Time Data/DCLK
Min.
CLOCKA/B Tmin
20
20
Typ.
244
488
244
Max.
CLOCKA/B Tmax
20
125000-244
50
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
40/83
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