AD5737 查看數據表（PDF） - Analog Devices
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AD5737 Datasheet PDF : 31 Pages
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AD5757/AD5737
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
RSETB 1
RSETA
2
REFGND 3
REFGND 4
AD0
5
AD1
6
SYNC
7
SCLK
8
SDIN
9
SDO
10
DVDD 11
DGND 12
LDAC
13
CLEAR 14
ALERT 15
FAULT 16
PIN 1
INDICATOR
64 LFCSP
48 COMPDCDC_C
47 IOUTC
46 VBOOSTC
45 AVCC
44 SWC
43 GND_SWC
42 GND_SWD
41 SWD
40 AVss
39 SWA
38 GND_SWA
37 GND_SWB
36 SWB
35 AGND
34 VBOOSTB
33 IOUTB
Figure 6. 64 LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic
Description
1
RSET_B
2
RSET_A
An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the
IOUT_B temperature drift performance. See the Features section.
An external, precision, low drift 15 k Ω current setting resistor can be connected to this pin to improve the
IOUT_A temperature drift performance. See the Features section.
3
REFGND
Ground Reference Point for Internal Reference.
4
REFGND
Ground Reference Point for Internal Reference.
5
ADO
Address decode for the DUT on the board.
6
AD1
Address decode for the DUT on the board.
7
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
8
SCLK
Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock
speeds of up to 30 MHz.
9
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
10
SDO
Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 3 and Figure 4.
11
DVDD
12
DGND
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
Digital Ground Pin.
13
LDAC
Load DAC. Active Low Input. This is used to update the DAC registers and consequently the analog
outputs. When tied permanently low the addressed DAC register is updated on the rising edge of SYNC. If
LDAC is held high during the write cycle the DAC input register is updated but the output update only
takes place at the falling edge of LDAC. See Figure 2. Using this mode all analog outputs can be updated
simultaneously. The LDAC pin must not be left unconnected.
14
CLEAR
Active High, Edge Sensitive Input. Asserting this pin sets the Output Current/Voltage to the pre-
programmed CLEAR CODE. Only channels enabled to be cleared will be cleared. See features section for
Rev. PrD | Page 10 of 31
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