MAX1007 查看數據表（PDF） - Maxim Integrated

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MAX1007

Mobile-Radio Analog Controller

Maxim Integrated 

Mobile-Radio Analog Controller

RSSI

The RSSI input provides a filtered input and a direct

input to the ADC. The filtered signal path consists of a

unity-gain buffer, an RC lowpass filter, and a peak

detector to condition the signal for the ADC. The low-

pass filter’s time constant is 10µs (min). The mux at the

ADC’s input selects CH0 (filtered input) or CH1 (direct

RSSI input).

Control Timing

The power-sense circuit is activated by the externally

generated PKWDW signal (Figure 1) when the

MAX1007 is either in transmit or receive mode. When

the PKWDW signal goes high, the entire power-sense

circuit turns on. However, since the PGA is active only

in the transmit mode, it remains shut down during RSSI

power measurements to conserve power.

Antenna Diversity

The antenna or preamble-switched diversity (PSD) cir-

cuit compares the signal amplitude presented at RSSI

during two different time periods and latches the result

at BANT (Best Antenna). The circuit consists of a dual

track/hold (T/H) stage, a comparator, and an output

latch (D flip-flop).

The comparison begins with the signal from the first

antenna applied to the RSSI pin (Figure 2). PSDWDW

goes high, and the PSD circuit is turned on. A power-

on-reset signal initializes the D flip-flop so that it always

starts with BANT low. After 4 clocks to reset the peak

detector, PSDCTRL goes high to start the measure-

ment. The T/H stage acquires the signal for 8 clocks

while PSDCTRL is high, then holds the peak value while

the second antenna is switched externally to the RSSI

pin and the T/H is zeroed. PSDCTRL goes low for

another 4 clocks, then goes high to enable the peak

detector again. The peak detector is active for another

8 clocks while the output is compared with the peak

value for the first antenna. When PSDWDW goes low at

the end of the comparison phase, the comparator’s out-

put is clocked into the D flip-flop. The D flip-flop’s out-

put, BANT, is low if the first antenna signal is greater

than the second, and high if the second signal is

greater than the first. PSDCTRL goes low one clock

period after PSDWDW goes low to power down the

PSD circuitry.

Analog-to-Digital Converter

The ADC is an 8-bit, half-flash ADC with a T/H and two

inputs (CH0, CH1). When selected, the acquisition time

is 1.74µs. The ADC input range is equal to the 1.028V

internal reference.

Reference

The bandgap voltage reference supports several

blocks of the MAX1007. The nominal 1.21V output is

scaled and buffered for the power-sense bias, the

PGA, the ADC, and the DACs. The PSBIAS output volt-

age is 1.87V nominal. The ADC reference is 1.028V. It

is buffered to isolate switching noise and to allow exter-

nal capacitor bypassing (0.014µF to 0.05µF) for AC sta-

bility. A buffered gain supplies all DACs with a nominal

2.42V reference voltage.

Digital-to-Analog Converters

All four DAC outputs are reset to zero at power-up.

Preset DACs to output voltages other than zero in total

shutdown mode and update DACs by settling the LD

bit in the command byte.

XDAC

XDAC is a 6-bit voltage-output DAC intended to drive

varactor diodes to tune a voltage-controlled crystal

oscillator. The input is double-buffered for independent

updates. The inverted R-2R ladder output is unbuffered

since the load is strictly capacitive. The maximum out-

put voltage is 2.42V nominal, and the maximum output

resistance is 30kΩ. The output is reset to zero at

power-up and is active instantly. When XDAC is dis-

abled, the DAC output is actively pulled to AGND.

GDAC

GDAC is a 6-bit voltage-output DAC intended to control

an external negative bias generator, such as the

MAX840, for a GaAs amplifier. The digital input is double-

buffered. The inverted R-2R ladder output is buffered

and can drive a 5kΩ load. The maximum output voltage

is 2.42V nominal. The DAC output is reset to zero at

power-up and is active in standby. A programmable

logic output (SDG) is provided to shut down the exter-

nal bias generator.

SDAC and KDAC

SDAC and KDAC are 7-bit voltage-output DACs intend-

ed to tune power levels of an up/downconverter or a

modulator. The digital inputs are double-buffered. The

inverted R-2R ladder outputs are buffered and can

drive 5kΩ loads. The maximum output voltage is 2.42V

nominal. The SDAC and KDAC DAC outputs are reset

to zero at power-up.

Serial-Interface and Control Logic

The serial interface is a 4-wire implementation with CS,

SCLK, and DIN inputs and a DOUT output. The hard-

ware consists of a 7-bit command register, an 8-bit

data input register, an 8-bit data output register, a

counter, and control logic. Communication is framed in

16-bit words (8 command bits followed by 8 data bits)

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