P89LPC9301(2009) 查看數據表（PDF） - NXP Semiconductors.

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P89LPC9301
(Rev.:2009)

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable flash

NXP Semiconductors. 

NXP Semiconductors

P89LPC9301/931A1

8-bit microcontroller with accelerated two-clock 80C51 core

I Serial flash In-System Programming (ISP) allows coding while the device is mounted

in the end application.

I In-Application Programming (IAP) of the flash code memory. This allows changing the

code in a running application.

I Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to ±5 %,

requiring no external components. The watchdog prescaler is selectable from

eight values.

I High-accuracy internal RC oscillator option, with clock doubler option, allows operation

without external oscillator components. The RC oscillator option is selectable and fine

tunable.

I Switching on the fly among internal RC oscillator, watchdog oscillator, external clock

source provides optimal support of minimal power active mode with fast switching to

maximum performance.

I Idle and two different power-down reduced power modes. Improved wake-up from

Power-down mode (a LOW interrupt input starts execution). Typical power-down

current is 1 µA (total power-down with voltage comparators disabled).

I Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A software reset function is also available.

I Configurable on-chip oscillator with frequency range options selected by user

programmed flash configuration bits. Oscillator options support frequencies from

20 kHz to the maximum operating frequency of 18 MHz.

I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator

allowing it to perform an oscillator fail detect function.

I Programmable port output configuration options: quasi-bidirectional, open drain,

push-pull, input-only.

I High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6,

P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is

specified for the entire chip.

I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of

the pins match or do not match a programmable pattern.

I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns

minimum ramp times.

I Only power and ground connections are required to operate the P89LPC9301/931A1

when internal reset option is selected.

I Four interrupt priority levels.

I Eight keypad interrupt inputs, plus two additional external interrupt inputs.

I Schmitt trigger port inputs.

I Second data pointer.

I Emulation support.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

© NXP B.V. 2009. All rights reserved.

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