PCA9516APW 查看數據表（PDF） - NXP Semiconductors.

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PCA9516APW

5-channel I2C-bus hub

NXP Semiconductors. 

NXP Semiconductors

PCA9516A

5-channel I2C-bus hub

The PCA9516A is 5.5 V tolerant so it does not require any additional circuitry to translate

between the different bus voltages.

When one side of the PCA9516A is pulled LOW by a device on the I2C-bus, a CMOS

hysteresis type input detects the falling edge and causes an internal driver on the other

side to turn on, thus causing the other side to also go LOW. The side driven LOW by the

PCA9516A will typically be at VOL = 0.5 V.

3.3 V

5V

SDA

SCL

BUS

MASTER

400 kHz

VCC

SDA0

SDA1

SCL0

SCL1

EN1

EN2

EN3

SDA2

EN4

SCL2

PCA9516A

SDA SLAVE 1

SCL 400 kHz

3.3 V

SDA SLAVE 2

SCL 400 kHz

5V

SDA3

SCL3

SDA SLAVE 3

SCL 100 kHz

3.3 V or 5 V

PCA9516A_3

Product data sheet

SDA4

SCL4

002aae617

Fig 5. Typical application

In order to illustrate what would be seen in a typical application, refer to Figure 6 and

Figure 7. If the bus master in Figure 5 were to write to the slave through the PCA9516A,

we would see the waveform shown in Figure 6 on Bus 0. This looks like a normal I2C-bus

transmission until the falling edge of the 8th clock pulse. At that point, the master releases

the data line (SDA) while the slave pulls it LOW through the PCA9516A. Because the VOL

of the PCA9516A is typically around 0.5 V, a step in the SDA will be seen. After the master

has transmitted the 9th clock pulse, the slave releases the data line.

On the Bus 1 side of the PCA9516A, the clock and data lines would have a positive offset

from ground equal to the VOL of the PCA9516A. After the 8th clock pulse, the data line will

be pulled to the VOL of the slave device that is very close to ground in our example.

It is important to note that any arbitration or clock stretching events on Bus 1 require that

the VOL of the devices on Bus 1 be 70 mV below the VOL of the PCA9516A (see VOL−VILc

in Section 9 “Static characteristics”) to be recognized by the PCA9516A and then

transmitted to Bus 0.

Rev. 03 — 23 April 2009

© NXP B.V. 2009. All rights reserved.

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