74V2T14(2003) 查看數據表（PDF） - STMicroelectronics
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74V2T14 Datasheet PDF : 7 Pages
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74V2T14
TRIPLE SCHMITT INVERTER
s HIGH SPEED: tPD = 5.0ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 1µA(MAX.) at TA = 25°C
s TYPICAL HYSTERESIS:
Vh=700mV at VCC=4.5V
s POWER DOWN PROTECTION ON INPUT
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8mA (MIN) at VCC = 4.5V
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 4.5V to 5.5V
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V2T14 is an advanced high-speed CMOS
TRIPLE SCHMITT INVERTER fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on input and 0
to 7V can be accepted on input with no regard to
SOT23-8L
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SOT23-8L
T&R
74V2T14STR
the supply voltage. This device can be used to
interface 5V to 3V. Pin configuration and function
are the same as those of the 74V2T04 but the
74V2T14 has hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
The input is equipped with protection circuits
against static discharge, giving it ESD immunity
and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 2003
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