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LNBS21PD(2002) 查看數據表(PDF) - STMicroelectronics

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LNBS21PD Datasheet PDF : 19 Pages
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LNBS21
TABLE A: PIN CONFIGURATIONS
SYMBOL
NAME
VCC Supply Input
GATE Exrernal Switch Gate
SENSE Current Sense Input
Vup Step-up Voltage
OUT Output Port
SDA Serial Data
SCL Serial Clock
DSQIN DiSEqC Input
DETIN Detector In
DSQOUT DiSEqC Output
EXTM Extrernal Modulator
GND Ground
BYP Bypass Capacitor
LT1 Loop Through Switch
LT2 Loop Through Switch
ADDR Address Setting
FUNCTION
8V to 15V supply. A 220µF bypass capacitor to
GND with a 470nF (ceramic) in parallel is
recommended
External MOS switch Gate connection of the
step-up converter
Current Sense comparator input. Connected to
current sensing resistor
Input of the linear post-regulator. The voltage on this
pin is monitored by internal step-ut controller to
keep a minimum dropout across the linear pass
transistor
Output of the linear post regulator modulator to the
LNB. See truth table for voltage selections.
Bidirectional data from/to I2C bus.
Clock from I2C bus.
When the TEN bit of the System Register is LOW,
this pin will accept the DiSEqC code from the main
µcontroller. The LNBS21 will use this code to
modulate the internally generated 22kHz carrier. Set
to GND thi pin if not used.
22kHz Tone Detector Input. Must be AC coupled to
the DiSEcQ bus.
Open collector output of the tone Detector to the
main µcontroller for DiSEcQ data decoding. It is
LOW when tone is detected.
External Modulation Input. Need DC decoupling to
the AC source. If not used, can be left open.
Circuit Ground. It is internally connected to the die
frame for heat dissipation.
Needed for internal preregulator filtering
In standby mode the power switch between LT1
and LT2 is closed. Max allowed current is 900mA.
this pin can be left open if loopthrough function is
not needed.
Same as above
Four I2C bus addresses available by setting the
Address Pin level voltage
PIN NUMBER
vs PACKAGE
18
17
16
19
2
12
13
14
9
15
5
1, 10, 11, 20
8
4
3
7
4/19

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