M29F016B 查看數據表（PDF） - STMicroelectronics
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M29F016B Datasheet PDF : 22 Pages
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M29F016B
Table 3. Uniform Block Addresses, M29F016B
#
Size
(Kbytes)
Address Range
Protection
Group
31
64
1F0000h-1FFFFFh
30
64
1E0000h-1EFFFFh
7
29
64
1D0000h-1DFFFFh
28
64
1C0000h-1CFFFFh
27
64
1B0000h-1BFFFFh
26
64
1A0000h-1AFFFFh
6
25
64
190000h-19FFFFh
24
64
180000h-18FFFFh
23
64
170000h-17FFFFh
22
64
160000h-16FFFFh
5
21
64
150000h-15FFFFh
20
64
140000h-14FFFFh
19
64
130000h-13FFFFh
18
64
120000h-12FFFFh
4
17
64
110000h-11FFFFh
16
64
100000h-10FFFFh
15
64
0F0000h-0FFFFFh
14
64
0E0000h-0EFFFFh
3
13
64
0D0000h-0DFFFFh
12
64
0C0000h-0CFFFFh
11
64
0B0000h-0BFFFFh
10
64
0A0000h-0AFFFFh
2
9
64
090000h-09FFFFh
8
64
080000h-08FFFFh
7
64
070000h-07FFFFh
6
64
060000h-06FFFFh
1
5
64
050000h-05FFFFh
4
64
040000h-04FFFFh
3
64
030000h-03FFFFh
2
64
020000h-02FFFFh
0
1
64
010000h-01FFFFh
0
64
000000h-00FFFFh
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/Busy
Output section, Table 14 and Figure 11, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at VID will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode, Auto Select
mode and Erase Suspend mode.
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