CS4954-CQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS4954-CQ Datasheet PDF : 56 Pages
| |||
CS4954 CS4955
tude levels. Table 7 shows the relationship of the
digital input signal and the analog output voltage.
Digital Input
0×38
0×3B
0×C4
Analog Output Voltage
286 mV
300 mV
1000 mV
Table 7. VBI Encoding Signal Amplitudes
Each LSB corresponds to a step of 5 mV in the out-
put voltage.
5.14. Super White/Super Black support
The ITU-R BT.601 recommendation limits the al-
lowed range for the digital video data between
0×10 - 0×EB for luma and between 0×10 - 0×F0 for
the chrominance values. This chip will clip any
digital input value which is out of this range to con-
form to the ITU-R BT.601 specifications.
However for some applications it is useful to allow
a wider input range. By setting the CLIP_OFF bit
(CONTROL_6 register) the allowed input range is
extended between 0×01 - 0×FE for both luma and
chrominance values.
Note that 0×00 and 0×FF values are never allowed,
since they are reserved for synchronization infor-
mation.
5.15. Interrupts
In order to better support precise video mode
switches and to establish a software/hardware
handshake with the closed caption insertion block
the CS4954/5 is equipped with an interrupt pin
named INT. The INT pin is active high. There are
three interrupt sources: VSYNC, Line 21, and Line
284. Each interrupt can be individually disabled
with the INT_EN Register. Each interrupt is also
cleared via writing a one to the corresponding
INT_CLR Register bits. The three individual inter-
rupts are OR-ed together to generate an interrupt
signal which is presented on the INT output pin. If
an interrupt has occurred, it cannot be eliminated
with a disable, it must be cleared.
5.16. General Purpose I/O Port
The CS4954/5 has a GPIO port and register that is
available when the device is configured for I2C
host interface operation. In I2C host interface
mode, the PDAT [7:0] pins are unused by the host
interface and they can operate as input or output
pins for the GPIO_DATA_REG Register (0×0A).
The CS4954/5 also contains the
GPIO_CTRL_REG Register (0×09) which is used
to configure the GPIO pins for input or output op-
eration.
The GPIO port PDAT [7:0] pins are configured for
input operation when the corresponding
GPIO_CTRL_REG [7:0] bits are set to 0. In GPIO
input mode, the CS4954/5 will latch the data on the
PDAT [7:0] pins into the corresponding bit loca-
tions of GPIO_DATA_REG when it detects regis-
ter address 0×0A through the I2C interface. A
detection of address 0×0A can happen in two ways.
The first and most common way this will happen is
when address 0×0A is written to the CS4954/5 via
its I2C interface. The second method for detecting
address 0×0A is implemented by accessing register
address 0×09 through I2C. In I2C host interface op-
eration, the CS4954/5 register address pointer will
auto-increment to address 0×0A after an address
0×09 access.
The GPIO port PDAT [7:0] pins are configured for
output operation when the corresponding
GPIO_CTRL_REG [7:0] bits are set. In GPIO out-
put mode, the CS4954/5 will output the data in
GPIO_DATA_REG [7:0] bit locations onto the
corresponding PDAT [7:0] pins when it detects a
register address 0×0A through the I2C interface.
26
DS278PP4
Share Link: 