CS4954-CQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS4954-CQ

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4954 CS4955

chrominance portion of the video signal (color

only). C is designed to drive proper video levels

into a 37.5 Ω load. Reference the detailed electrical

section of this data sheet for the exact C digital to

analog AC and DC performance data. A EN_C en-

able control register bit in the Control Register 1

(0×05) is provided to enable or disable the chromi-

nance DAC. For a complete disable and lower

power operation the chrominance DAC can be to-

tally shut down via the SVIDCHR_PD register bit

in the Control Register 4 (0×04). In this mode turn-

on through the control register will not be instanta-

neous.

7.4.3. CVBS DAC

The CVBS pin is driven from a 10-bit 27 MHz cur-

rent output DAC that internally receives a com-

bined luma and chroma signal to provide

composite video output. CVBS is designed to drive

proper composite video levels into a 37.5 Ω load.

Reference the detailed electrical section of this data

sheet for the exact CVBS digital to analog AC and

DC performance data. The EN_COM enable con-

trol register bit, in Control Register 1 (0×05), is

provided to enable or disable the output pin. When

disabled, there is no current flow from the output.

For a complete disable and lower power operation,

the CVBS37 DAC can be totally shut down via the

COMDAC_PD control register bit in Control

Register 4 (0×04). In this mode turn-on through the

control register will not be instantaneous.

7.4.4. Red DAC

The Red pin is driven from a 10-bit 27 MHz current

output DAC that internally receives a combined

luma and chroma signal to provide composite vid-

eo output. Red is designed to drive proper compos-

ite video levels into a 37.5 Ω load. Reference the

detailed electrical section of this data sheet for the

exact red digital to analog AC and DC performance

data. The EN_R enable control register bit, in Con-

trol Register 1 (0×05), is provided to enable or dis-

able the output pin. When disabled, there is no

current flow from the output. For a complete dis-

able and lower power operation, the red DAC can

be totally shut down via the R_PD control register

bit in Control Register 4 (0×04). In this mode turn-

on through the control register will not be instanta-

neous.

7.4.5. Green DAC

The green pin is driven from a 10-bit 27 MHz cur-

rent output DAC that internally receives a com-

bined luma and chroma signal to provide

composite video output. Green is designed to drive

proper composite video levels into a 37.5 Ω load.

Reference the detailed electrical section of this data

sheet for the exact green digital to analog AC and

DC performance data. The EN_G enable control

register bit, in Control Register 1 (0×05), is provid-

ed to enable or disable the output pin. When dis-

abled, there is no current flow from the output. For

a complete disable and lower power operation, the

green DAC can be totally shut down via the G_PD

control register bit in Control Register 4 (0×04). In

this mode turn-on through the control register will

not be instantaneous.

7.4.6. Blue DAC

The blue pin is driven from a 10-bit 27 MHz cur-

rent output DAC that internally receives a com-

bined luma and chroma signal to provide

composite video output. Blue is designed to drive

proper composite video levels into a 37.5 Ω load.

Reference the detailed electrical section of this data

sheet for the exact blue digital to analog AC and

DC performance data. The EN_B enable control

register bit, in Control Register 5 (0×05), is provid-

ed to enable or disable the output pin. When dis-

abled, there is no current flow from the output. For

a complete disable and lower power operation, the

blue DAC can be totally shut down via the B_PD

control register bit in Control Register 4 (0×04). In

this mode turn-on through the control register will

not be instantaneous.

DS278PP4

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