CS4954-CQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS4954-CQ

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4954 CS4955

Control Register 0

Address

Bit Number

Bit Name

Default

0×00

7

0

CONTROL_0 Read/Write

6

5

TV_FMT

0

0

4

MSTR

0

Default Value = 01h

3

CCIR656

0

2

PROG

0

1

IN_MODE

0

0

CBCR_UV

1

Bit

Mnemonic

Function

selects the TV display format

000:

NTSC-M CCIR601 timing (default)

001:

NTSC-M RS170A timing

010:

7:5

TV_FMT

011:

PAL-B, D, G, H, I

PAL-M

100:

PAL-N (Argentina)

101:

PAL-N (non Argentina)

110-111:

reserved

4

MSTR

1 = Master Mode, 0 = Slave Mode

3

CCIR656 video input is in ITU R.BT656 format (0 = off, 1 = on)

2

PROG

Progressive scanning enable (enable = 1)

1

IN_MODE Input select (0 = solid background, 1 = use V [7:0] data)

0

CBCR_UV enable YCbCr to YUV conversion (1 = enable, 0 = disable)

Control Register 1

Address

Bit Number

Bit Name

Default

0×01

CONTROL_1 Read/Write

7

6

LUM DEL

0

0

5

CH BW

0

4

LPF_ON

0

Default Value = 02h

3

2

RGB_BW

FLD

0

0

1

PED

1

0

CBCRSEL

0

Bit

Mnemonic

Function

luma delay on the composite1 output

00:

no delay (default)

7:6

LUM DEL 01:

1 pixel clock delay

10:

2 pixel clock delay

11:

3 pixel clock delay

5

CH BW

chroma lpf bandwidth (0 = 650 kHz, 1 = 1.3 Mhz)

4

LPF ON chroma lpf on/off (0 = off, 1 = on)

3

RGB_BW 0 = Full bandwidth on RGB, 1 = BW reduced to 2.5 MHz (3 dB point) (default 0)

2

FLD_POL Polarity of Field (0: odd field = 0,1: odd field = 1)

1

PED

Pedestal offset (0: 0 IRE, 1: 7.5 IRE)

0

CBCRSEL CbCr select (0 = chroma undelayed, 1 = chroma delayed by one clock)

36

DS278PP4

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