CS4954-CQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CS4954-CQ Datasheet PDF : 56 Pages
| |||
CS4954 CS4955
WR
ADDR
Twpw
Twr
Twac
PDAT[7:0]
Tas
Twds Twdh
Figure 29. 8-bit Parallel Host Port Timing: Address Write Cycle
8.2. Register Description
A set of internal registers are available for control-
ling the operation of the CS4954/5. The registers
extend from internal address 0×00 through 0×5A.
Table 9 shows a complete list of these registers and
their internal addresses. Note that this table and the
subsequent register description section describe the
full register map for the CS4954 only. A complete
CS4955 register set description is available only to
Macrovision ACP-PPV Licensed Buyers.
8.2.1. Control Registers
Address
0×00
0×01
0×02
0×03
0×04
0×05
0×06
0×07
0×08
0×09
0×0A
0×0B
0×0C
0×0D
0×0E
0×0F
0×10
0×11
0×12
0×13
0×14
0×15
0×16
Register Name
control_0
control_1
control_2
control_3
control_4
control_5
control_6
RESERVED
bkg_color
gpio_ctrl_reg
gpio_data_reg
RESERVED
RESERVED
SYNC_0
SYNC_1
I2C_ADR
SC_AMP
SC_SYNTH0
SC_SYNTH1
SC_SYNTH2
SC_SYNTH3
HUE_LSB
HUE_MSB
Table 9. Control Registers
Type
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Default value
01h
02h
00h
00h
3Fh
00h
00h
03h
00h
00h
90h
F4h
00h
1Ch
3Eh
F8h
E0h
43h
00h
00h
34
DS278PP4
Share Link: 